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Integrated Circuit Topography Regulations (SOR/93-212)

Regulations are current to 2026-09-30 and last amended on 2024-01-01. Previous Versions

 Where a topography that consists of more than two layers contains confidential information, an application may contain, instead of a complete set of overlay sheets, drawings or photographs as required by section 14, a set that contains the same total number of sheets, drawings or photographs, but that includes a selected number of sheets, drawings or photographs on which is blocked out up to 50 per cent of the total area covered by those sheets, drawings or photographs, if

  • (a) the selected sheets, drawings or photographs are clearly indicated in the application;

  • (b) the number of sheets, drawings or photographs selected does not exceed 50 per cent of the total number of sheets, drawings or photographs, said total number having been reduced by one where it is an odd number; and

  • (c) the application contains topography design data in printed form for the areas that are blocked out; however, up to 50 per cent of these data may be blocked out, if the application contains four or more integrated circuit products incorporating the topography.

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